It has been long considered that it is more difficult to obtain a high reverse blocking voltage in a planar semiconductor device than in a mesa semiconductor device. Accordingly, to increase the planar semiconductor device resistance to high voltage, many proposals have been made. One of these proposals is to provide a guard ring, and another is to provide a field plate. Recently a mold packaged voltage-resistant element has become popular because of its high breakdown resistance to a voltage of not smaller than 1,000 v. However, the most important thing is not that the element can withstand such a high voltage, but that it can be mass-procuced without losing its high breakdown resistance and reliability. In this respect the planar semiconductor device has been found to be basically superior to the mesa semiconductor device.
In general, the voltage breakdown resistance of semiconductor devices depends on how to evenly reduce the intensity of electric field at the junction where a high voltage is maintained. This idea is not only applicable to a planar semiconductor device but also to a mesa semiconductor device. In fact, by applying this idea to mesa semiconductor devices they have been found to withstand high voltages of 10,000 v or more. In this case, however, considerably elaborate construction is required for bevelling or coating with plastic in a bevelled part. In addition, bevelling is required in a relatively vast area around the chip. Such requirements make mass-production impossible or difficult to carry out. Furthermore, when mesa semiconductor devices are produced in this way, it has been found that they do not exhibit a sufficient reliability in a high temperature reverse bias blocking test conducted on a DC source of supply. Alternatively, the glassivation process, in which a powdered glass is sintered in grooves formed at the junctions, finds itself applicable for mass-production, and also effective to solve the problem of unstability involved in the plastic sealing. However, disadvantages have been also found; one is the insufficient dispersion of electric field at the junction resulting from the difficulty of forming side walls of the grooves at an inclination of more than 90.degree. to the junction. Another is the localizing or partial intensifying of electric fields, which results from a requirement relating to the layers of high resistivity, requiring their thickness to be as thin as possible for transistors, or high quality diodes which is not applicable to an ordinary class of transistors, or diodes. However, as well known, a thin layer tends to cause the electric field to intensify. Accordingly, it is impractical when the voltages to be applied to is 1,000 v or more. Furthermore, no improvement has been found in high temperature DC reverse bias blocking ability.
In contrast, the planar semiconductor devices, in principle, allows a relatively large space for the electric fields. Accordingly, if the detrimental localizing of electric field is avoided, it is possible to construct such planar semiconductor devices which can constantly withstand high voltages. In fact, however, it is not easy to achieve this objective due to the likelihood that the electric fields will intensify partially around the junction between the silicon substrate and the silicon dioxides layer, wherein the degree of the intensifying of electric field varies with production factors. The guard rings or the field plates are effective to reduce the degree of the intensifying of electric field in this area. In addition, when this type of planar semiconductor devices are subjected to a high temperature reverse bias blocking test conducted on a DC source of supply, an inversion is likely to occur in the silicon surface due to a potential difference between the surface and the undersurface of the layers, whereby the reverse blocking voltage is stepped up. This shows that some cause or other inherently exists for enhancing the voltage breakdown resistance.
To exemplify the principle of this phenomenon, reference will be more particularly made to FIG. 1, in which FIG. 1 (a) shows a cross-section on an enlarged scale of part of a silicon chip, prior to a high temperature reverse bias blocking, and in which FIG. 1 (b) is a diagrammatic view showing potentials in the surface of the silicon chip. The reference numeral 1 designates an insulating layer, and the reference numeral 2 designates a depletion layer. The reference numeral 3 designates a channel stop (N.sup.+) region, and the reference numeral 4 designates a N.sup.- layer. The reference numeral 5 designates a P- layer, and the reference character J1 designates a p-n junction at which the N.sup.- layer 4 and the P- layer 5 meet. In FIG. 1 (b) the vertical axis represents the electric potentials, and the horizontal axis represents the distances on the surface from the p-n junction, which consists of the P- layer 5 and the N.sup.- layer 4. The curve A represents the potentials in the surface of the high resistivity region, that is, the N.sup.- layer 4 (the undersurface of the insulating layer) and the curve B represents potentials in the surface of the insulating layer 1. The potential in the surface of the insulating layer 1 depends on the electric conductivity of the bulk of the insulating layer 1, and that of the surface thereof. If the electric conductivity of the surface of the layer 1 is slightly higher than that of the bulk of this layer, a potential difference occurs between the surface and the undersurface of the layer due to a difference between the potential distribution in the surface of the insulating layer 1 and that in the depletion layer 2. This is likely to cause an inversion in the region of high resistivity. A condition at which the surface of the insulating layer becomes slightly electrically conductive rarely occurs when the silicon chip is canned at a dry atmosphere, but it is likely to happen if the chip is sealed in a gel-like substance. In this case the depletion layer tends to extend, and the reverse blocking voltage becomes higher. Eventually, it may reach a stage at which the electric potential in an area adjacent to the channel stop region in the neighborhood of the chip becomes high, and a yielding may arise in this area. This phenomenon more readily occurs when the resistivity of the high resistivity region becomes higher, or when a higher voltage is impressed for conducting the blocking test. This will be fatal to a planar semiconductor device having a plastic sealing which only allows reverse blocking voltages of 500 v or around.
FIG. 2 (a) and (b) show a cross-section on an enlarged scale of part of a silicon chip, and electric potentials in the surface of the chip, respectively. In FIG. 2 (b) the vertical axis represents the electric potentials, and the horizontal axis represents the distances on the surface from the p-n junction, which consists of the P- layer 5 and the N.sup.- layer 4, wherein the curve A represents the potential in the surface of high resistivity region 4, and wherein the curve B represents the potentials in the surface of the insulating layer 1. The curve C represents the electric fields in the horizontal direction in the neighborhood of the surface of the high resistivity region. The area D in FIG. 2 (a) represents a region in which an inversion is caused due to a potential difference between the surface and the undersurface of the insulating layer.
Referring to FIG. 3 (a) and (b), we will describe how to prevent the occurrence of a yielding in an area adjacent to the channel stop region around the chip. As shown in FIG. 3 (a), the channel stop region 3 is provided with an electrode 6, which, as a result of blocking tests, has been found to exhibit satisfactory results on the voltage breakdown resistance. In FIG. 3 (b), the curve A represents the potentials in the surface of the high resistivity region 4, the curve B represents the potentials in the surface of the insulating layer 1, and the curve C reprsents the electric fields expected in the surface of the high resistivity region 4. The newly provided electrode 6 affects the distrbutions of the potentials and electric fields represented by the curves A, and C respectively whereby the inversion area D is shortened in length to thereby reduce the intensifying of the electric field around the channel stop region to a greater extent. It will be understood from this that in order to secure a high reliability in the planar semiconductor devices of a high-voltage breakdown resistance it is essential to control the electric potentials between the surface and the undersurface of the insulating layer on the surface of the element. As a practical version, however, at least one guard ring or where necessary, several guard rings 11a, 11b . . . are provided as shown in FIG. 4 (a). If the main junction J1 alone is employed with no guard ring as shown in FIG. 1 (a), FIG. 2 (a) and FIG. 3 (a), it will be impossible to obtain the desired values for voltage breakdown resistance. In FIG. 4 (b) the curve A represents the potentials in the surface of the high resistivity region 4, the curve B represents the potentials in the surface of the insulating layer 1, and the curve E represents the potential difference between the surface and the undersurface of the insulating layer 1, expressed by: E=B-A. The guard ring is originally intended to prevent the localizing of electric field in the surface, but it is additionally effective to reduce the difference in potential between the surface and the undersurface of the insulating layer 1, which will be appreciated from FIG. 4 (b). This secures the reliability, particularly in devices which have a voltage breakdown resistance of about 500 v.
This use of one or more guard rings is applicable to a conventional type of high-voltage resistible planar semiconductor device so as to reduce the difference in potential between the surface and the undersurface of the insulating layer. This secures the reliabilty of devices which have a voltage breakdown resistance of around 500 v. However, it is not applicable to devices which have a voltage breakdown resistance of higher than 1000 v, because of the unstable factors involved in sealing with plastic.